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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
1.0 Features
Primary-side feedback eliminates opto-isolators and simplifies design Quasi-resonant operation for highest overall efficiency EZ-EMI (R) design to easily meet global EMI standards Up to 130 kHz switching frequency enables small adapter size Very tight LED constant current regulation No external compensation components required Built-in output constant-current control with primary-side feedback for LED driver. Low start-up current (10 A typical) Built-in soft start Built-in short circuit protection and output overvoltage protection Current sense resistor short protection Overtemperature Protection Open circuit protection Universal input range from 85 Vac to 264 Vac Single-fault protection Small input bulk capacitor Long MTBF High efficiency
L
2.0 Description
The IW3620 is a high performance AC/DC offline LED driver which uses digital control technology to build peak current mode PWM flyback power supplies. The device operates in quasi-resonant mode at heavy load to provide high efficiency along with a number of key built-in protection features while minimizing the external component count, simplifying EMI design and lowering the total bill of material cost. The IW3620 removes the need for secondary feedback circuitry while achieving excellent line and load regulation. It also eliminates the need for loop compensation components while maintaining stability over all operating conditions. Pulse-bypulse waveform analysis allows for a loop response that is much faster than traditional solutions, resulting in improved dynamic load response. The built-in current limit function enables optimized transformer design in universal off-line applications over a wide input voltage range.
3.0 Applications
LED lighting
VOUT + N +
+ RTN
1 2 3 4
NC VSENSE VIN SD
VCC 8 OUTPUT 7 ISENSE 6 GND 5
Optional NTC Thermistor
U1 IW3620
Figure 3.1 : Typical Application Circuit
Rev. 1.3
IW3620 10/1/09
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
4.0 Pinout Description
1 2 3 4
IW3620
NC VSENSE VIN SD VCC OUTPUT ISENSE GND
8 7 6 5
Pin #
1 2 3 4 5 6 7 8
Name NC
VSENSE VIN SD GND ISENSE OUTPUT VCC
Type
-
Pin Description
No connection.
Analog Input Auxiliary voltage sense (used for primary side regulation). Analog Input Rectified AC line average voltage sense. Analog Input Ground External shutdown control. Connect to ground through a resistor if not used. (see section 10.16) Ground.
Analog Input Primary current sense (used for cycle-by-cycle peak current control and limit). Output Power Input Gate drive for external MOSFET switch. Power supply for control logic and voltage sense for power-on reset circuitry.
5.0 Absolute Maximum Ratings
Absolute maximum ratings are the parameter values or ranges which can cause permanent damage if exceeded. For maximum safe operating conditions, refer to Electrical Characteristics in Section 6.0.
Parameter
DC supply voltage range (pin 8, ICC = 20mA max) DC supply current at VCC pin Output (pin 7) VSENSE input (pin 2, IVsense 10 mA) VIN input (pin 3) ISENSE input (pin 6) SD input (pin 4) Power dissipation at TA 25C Maximum junction temperature Storage temperature Lead temperature during IR reflow for 15 seconds Thermal Resistance Junction-to-Ambient ESD rating per JEDEC JESD22-A114 Latch-Up test per JEDEC 78 Rev. 1.3 IW3620 10/1/09
Symbol
VCC ICC
Value
-0.3 to 18 20 -0.3 to 18 -0.7 to 4.0 -0.3 to 18 -0.3 to 4.0 -0.3 to 18
Units
V mA V V V V V mW C C C C/W V mA Page 2
PD TJ MAX TSTG TLEAD
526 125 -65 to 150 260 160 2,000 100
JA
IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
6.0 Electrical Characteristics
VCC = 12 V, -40C TA 85C, unless otherwise specified (Note 1)
Parameter
VIN SECTION (Pin 3) Start-up low voltage threshold Start-up current Input impedance VSENSE SECTION (Pin 2) Input leakage current Nominal voltage threshold Output OVP threshold OUTPUT SECTION (Pin 7) Output low level ON-resistance Output high level ON-resistance Rise time (Note 2) Fall time (Note 2) Maximum switching frequency VCC SECTION (Pin 8) Maximum operating voltage Start-up threshold Undervoltage lockout threshold Operating current
Symbol
VINSTLOW IINST ZIN IBVS VSENSE(NOM) VSENSE(MAX) RDS(ON)LO RDS(ON)-HP tR tF fSW(MAX)
Test Conditions
TA= 25C, positive edge VIN = 10 V, CVCC = 10 F After start-up
Min
335
Typ
369 10 5
Max
406 15
Unit
mV A kW
VSENSE = 2 V TA=25C, negative edge TA=25C, negative edge ISINK = 5 mA ISOURCE = 5 mA TA = 25C, CL = 330 pF 10% to 90% TA = 25C, CL = 330 pF 90% to 10% Any combination of line and load 1.523 1.790 1.538 1.846
1 1.553 1.900
A V V
40 102 200 40 130 300 60 140
W W ns ns kHz
VCC(MAX) VCC(ST) VCC(UVL) ICCQ VCC rising VCC falling CL = 330 pF, VSENSE = 1.5 V 10.8 5.5 12 6.0 3.5
16 13.2 6.6
V V V mA
Rev. 1.3
IW3620 10/1/09
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
6.0 Electrical Characteristics (cont.)
VCC = 12 V, -40C TA 85C, unless otherwise specified (Note 1)
Parameter
ISENSE SECTION (Pin 6) Peak limit threshold Isense short protection reference CC regulation threshold limit SD SECTION (Pin 4) Shutdown threshold Shutdown threshold in Startup Input leakage current Pull down resistance Pull up current source
Symbol
VPEAK VRSNS VREG-TH
Test Conditions
Min
Typ
1.1 0.15 1.0
Max
Unit
V V V
VSD-TH VSD-TH(ST) IBVSD RSD ISD VSD = 1.0 V
0.95
1.0 1.2
1.05
V V
1 7916 96 8333 107 8750 118
A W A
Notes: Note 1. Adjust VCC above the start-up threshold before setting at 12 V. Note 2. These parameters are not 100% tested, guaranteed by design and characterization. Note 3. Operating frequency varies based on the line and load conditions, see Theory of Operation for more details.
Rev. 1.3
IW3620 10/1/09
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
7.0 Typical Performance Characteristics
VCC Supply Start-up Current (A)
VCC Start-up Threshold (V)
9.0
12.2
6.0
12.0
3.0
11.8
0.0 0.0
2.0
4.0
8.0 6.0 VCC (V)
10.0
12.0
14.0
11.6 -50
-25
Ambient Temperature (C)
0
25
50
75
100
125
Figure 7.1 : VCC Supply Current vs. VCC
% Deviation of Switching Frequency from Ideal
Figure 7.2 : Start-Up Threshold vs. Temperature
0.3 %
-0.3 %
-0.9 %
-1.5 % -50
-25
Ambient Temperature (C)
0
25
50
75
100
125
Internal Reference Voltage (V)
1.548
1.538
1.528
1.518 -50
-25
Ambient Temperature (C)
0
25
50
75
100
125
Figure 7.3 : Switching Frequency % Change vs. Temperature
Figure 7.4 : Internal Reference vs. Temperature
Rev. 1.3
IW3620 10/1/09
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
8.0 Functional Block Diagram
VIN
3
8
VCC
ENABLE ZVin 5 k VIN_A 0.2 V ~ 2.0 V ADC
ENABLE
Start-up
VSENSE
2
ISD
Signal Conditioning
VVMS VFB Detection Switch
Digital Logic Control
Gate Driver 60 k
7
OUTPUT
6
4
RSD GND
5
Figure 8.1 : IW3620 Functional Block Diagram
9.0 Theory of Operation
The IW3620 is a digital controller which uses a proprietary primary-side control technology to eliminate the optoisolated feedback and secondary regulation circuits required in traditional designs. This results in a low-cost solution for AC/DC adapters. The IW3620 uses Critical Discontinuous Conduction Mode (CDCM) or Pulse Width Modulation (PWM) mode at high output power levels and switches to Pulse Frequency Modulation (PFM) mode at light load to minimize power dissipation to meet EPA 2.0 specification. Furthermore, iWatt's digital control technology enables fast dynamic response, tight output regulation, and full featured circuit protection with primary-side control. Referring to the block diagram in Figure 8.1, the digital logic control block generates the switching on-time and off-time information based on the line voltage and the output voltage feedback signal and provides commands to dynamically control the external MOSFET current. The system loop is compensated internally by a digital error amplifier. Adequate system phase and gain margin are guaranteed by design and no external analog components are required for loop compensation. The IW3620 uses an advanced digital Rev. 1.3 control algorithm to reduce system design time and improve reliability. Furthermore, accurate secondary constant-current operation is achieved without the need for any secondary-side sense and control circuits. The built-in protection features include overvoltage protection (OVP), output short circuit protection (SCP) and soft-start, AC line brown out, overcurrent protection, and Isense fault protection. Also the IW3620 automatically shuts down if it detects any of its sense pins to be either open or short. iWatt's digital control scheme is specifically designed to address the challenges and trade-offs of power conversion design. This innovative technology is ideal for balancing new regulatory requirements for green mode operation with more practical design considerations such as lowest possible cost, smallest size and highest performance output control.
-
VSD-TH
+
SD
DAC IPEAK VIPK 0V~1V
+ --
IW3620 10/1/09
-
VOCP
1.1 V
ISENSE
+
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver 9.1 Pin Detail
Pin 2 - VSENSE Sense signal input from auxiliary winding. This provides the secondary voltage feedback used for output regulation. Pin 3 - ViN Sense signal input from the rectified line voltage. VIN is used for line regulation. The input line voltage is scaled down using a resistor network. It is used for input undervoltage and overvoltage protection. This pin also provides the supply current to the IC during start-up. Pin 4 - SD External shutdown control. If the shutdown control is not used, this pin should be connected to GND via a resistor. Pin 5 - GND Ground. Pin 6 - iSENSE Primary current sense. Used for cycle by cycle peak current control. Pin 7 - OUTPUT Gate drive for the external MOSFET switch. Pin 8 - VCC Power supply for the controller during normal operation. The controller will start up when VCC reaches 12 V (typical) and will shut-down when the VCC voltage is below 6 V (typical). A decoupling capacitor should be connected between the VCC pin and GND.
vin(t) - TS(t)
Q1
off so that the VCC capacitor can be charged up again towards the start-up threshold.
Start-up Sequencing
VIN VCC(ST)
VCC
ENABLE
Figure 9.1 : Start-up Sequencing Diagram
9.3 Understanding Primary Feedback
Figure 9.2 illustrates a simplified flyback converter. When the switch Q1 conducts during tON(t), the current ig(t) is directly drawn from rectified sinusoid vg(t). The energy Eg(t) is stored in the magnetizing inductance LM. The rectifying diode D1 is reverse biased and the load current IO is supplied by the secondary capacitor CO. When Q1 turns off, D1 conducts and the stored energy Eg(t) is delivered to the output.
iin(t) + ig(t)
N:1 D1
id(t)
VO
+
vg(t)
CO
IO
VAUX VAUX
9.2 Start-up
Prior to start-up the VIN pin charges up the VCC capacitor through the diode between VIN and VCC (see Figure 8.1). When VCC is fully charged to a voltage higher than the startup threshold VCC(ST), the ENABLE signal becomes active and enables the control logic; the VIN switch turns on, and the analog-to-digital converter begins to sense the input voltage. Once the voltage on the VIN pin is above VINSTLOW, the IW3620 commences soft start function. An adaptive soft-start control algorithm is applied at startup state, during which the initial output pulses will be small and gradually get larger until the full pulse width is achieved. The peak current is limited cycle by cycle by Ipeak comparator. If at any time the VCC voltage drops below VCC(UVL) threshold then all the digital logic is reset. At this time VIN switch turns Rev. 1.3
Figure 9.2 : Simplified Flyback Converter
In order to tightly regulate the output voltage, the information about the output voltage and load current needs to be accurately sensed. In the DCM flyback converter, this information can be read via the auxiliary winding. During the Q1 on-time, the load current is supplied from the output filter capacitor CO. The voltage across LM is vg(t), assuming the voltage dropped across Q1 is zero. The current in Q1 ramps up linearly at a rate of: dig (t ) dt = vg (t ) LM (9.1)
At the end of on-time, the current has ramped up to:
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Digital PWM Current-Mode Controller for AC/DC LED Driver
ig _ peak (tON ) = vg (t ) x tON LM (9.2) represents the output voltage and is used to regulate the output voltage.
This current represents a stored energy of: L Eg = M x ig _ peak (tON ) 2 2 (9.3)
9.4 Constant Voltage Operation
After soft-start has been completed, the digital control block measures the output conditions. It determines output power levels and adjusts the control system according to a light load or a heavy load. If this is in the normal range, the device operates in the Constant Voltage (CV) mode, and changes the pulse width (TON), and off time (TOFF) in order to meet the output voltage regulation requirements. During this mode the PWM switching frequency is between 30 kHz and 130 kHz, depending on the line and load conditions. If less than 0.2 V is detected on VSENSE it is assumed that the auxiliary winding of the transformer is either open or shorted and the IW3620 shuts down.
When Q1 turns off, ig(t) in LM forces a reversal of polarities on all windings. Ignoring the communication-time caused by the leakage inductance LK at the instant of turn-off, the primary current transfers to the secondary at a peak amplitude of: id (t ) = NP x ig _ peak (tON ) NS
(9.4)
Assuming the secondary winding is master and the auxiliary winding is slave.
VAUX = VO x NAUX NS
9.5 Dynamic Load Transient
There are two components that compose the voltage drop during a load transient event. VDROP(sense) is the drop in voltage before the VSENSE signal is able to show a significant drop in output voltage. This is determined by Vmin or the reference voltage at which a load transient is detected. The smaller the Vmin is the smaller this drop in voltage is.
VDROP ( sense ) = VSENSE ( nom ) - VSENSE (min) x
VAUX
0V
(
)
VAUX = -VIN x
NAUX NP
VOUT VSENSE ( nom )
(9.7)
Figure 9.3 : Auxiliary Voltage Waveforms
Keep in mind that a smaller Vmin is less tolerant of noise and distortions in VSENSE than a larger one. The final drop in voltage is due to the time from when VSENSE drops Vmin to when the next VSENSE signal appears. In the worst case condition this is how much voltage drops during the longest switching period.
VDROP ( IC ) = I OUT x TP (No load) COUT
The auxiliary voltage is given by: VAUX = N AUX (VO + V ) NS (9.5)
and reflects the output voltage as shown in Figure 9.3. The voltage at the load differs from the secondary voltage by a diode drop and IR losses. The diode drop is a function of current, as are IR losses. Thus, if the secondary voltage is always read at a constant secondary current, the difference between the output voltage and the secondary voltage will be a fixed V. Furthermore, if the voltage can be read when the secondary current is small; for example, at the knee of the auxiliary waveform (see Figure 9.3), then V will also be small. With the IW3620, V can be ignored. The real-time waveform analyzer in the IW3620 reads the auxiliary waveform information cycle by cycle. The part then generates a feedback voltage VFB. The VFB signal precisely Rev. 1.3
(9.8)
A larger output capacitance in this case greatly reduces the VDROP(IC).
9.6 Valley Mode Switching
In order to reduce switching losses in the MOSFET and EMI, the IW3620 employs valley mode switching when IOUT is above 50%. In valley mode switching, the MOSFET switch is turned on at the point where the resonant voltage across the drain and source of the MOSFET is at its lowest point (see Figure 9.4). By switching at the lowest VDS, the switching loss will be minimized. Page 8
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver 9.8 PFM Mode at Light Load
Gate
VDS
Figure 9.4 : Valley Mode Switching
Turning on at the lowest VDS generates lowest dV/dt, thus valley mode switching can also reduce EMI. To limit the switching frequency range, the IW3620 can skips valleys (seen in the first cycle in Figure 9.4) when the switching frequency becomes too high. IW3620 provides valley mode switching during constant output operation. So, the EMI and switching losses are still minimized during CC mode. This feature is superior to other quasi-resonant technologies which only support valley mode switching during constant voltage operation. This is beneficial to LED driver applications where the IC mainly operates in CC mode.
The IW3620 normally operates in a fixed frequency PWM or critical discontinuous conduction mode when IOUT is greater than approximately 10% of the specified maximum load current. As the output load IOUT is reduced, the on-time tON is decreased. At the moment that the load current drops below 10% of nominal, the controller transitions to Pulse Frequency Modulation (PFM) mode. Thereafter, the ontime will be modulated by the line voltage and the off-time is modulated by the load current. The device automatically returns to PWM mode when the load current increases.
9.9 Variable Frequency Operation
At each of the switching cycles, the falling edge of VSENSE will be checked. If the falling edge of VSENSE is not detected, the off-time will be extended until the falling edge of VSENSE is detected. The maximum allowed transformer reset time is 75 s for IW3620.
9.10 internal Loop Compensation
The IW3620 incorporates an internal Digital Error Amplifier with no requirement for external loop compensation. For a typical power supply design, the loop stability is guaranteed to provide at least 45 degrees of phase margin and -20dB of gain margin.
9.7 Constant Current Operation
The constant current mode (CC mode) maintains a constant current output. During this mode of operation the IW3620 will regulate the output current at a constant level regardless of the output voltage, while avoiding continuous conduction mode. To achieve this regulation the IW3620 senses the load current indirectly through the primary current. The primary current is detected by the ISENSE pin through a resistor from the MOSFET source to ground.
CV mode
9.11 Voltage Protection Functions
The IW3620 includes a function that protects against an output overvoltage (OVP). The output voltage is monitored by the VSENSE pin. If the voltage at this pin exceed its overvoltage threshold the IW3620 shuts down immediately. However, the IC remains biased which discharges the VCC supply. Once VCC drops below the UVLO threshold, the controller resets itself and then initiates a new soft-start cycle. The controller continues attempting start-up until the fault condition is removed.
VNOM
Output Voltage
9.12 PCL, OC and SRS Protection
Peak-current limit (PCL), over-current protection (OCP) and sense-resistor short protection (SRSP) are features built-into the IW3620. With the ISENSE pin the IW3620 is able to monitor the primary peak current. This allows for cycle by cycle peak current control and limit. When the primary peak current multiplied by the ISENSE sense resistor is greater than 1.1 V over current is detected and the IC will immediately turn off the gate drive until the next cycle. The output driver will send out switching pulse in the next cycle, and the switching pulse will continue if the OCP threshold is not reached; or, the switching pulse will turn off again if the OCP threshold is still reached. IW3620 10/1/09 Page 9
CC mode
Output Current
Figure 9.5 : Power Envelope
IOUT(CC)
Rev. 1.3
IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
If the ISENSE sense resistor is shorted there is a potential danger of the over current condition not being detected. Thus the IC is designed to detect this sense-resistor-short fault after the start up, and shutdown immediately. The VCC will be discharged since the IC remains biased. Once VCC drops below the UVLO threshold, the controller resets itself and then initiates a new soft-start cycle. The controller continues attempting start-up, but does not fully start-up until the fault condition is removed.
9.13 Shutdown
The shutdown (SD) pin in the IW3620 provides protection against overtemperature (OTP) and additional overvoltage (OVP) for the power supply. The IW3620 switches between monitoring overtemperature fault and overvoltage fault. In order to detect the resistance in the NTC for an overtemperature fault, the IW3620 connects a current source to the SD pin and checks the voltage on the pin. To ensure that the current source is settled before the voltage is checked both OTP and OVP are detected on the last cycle, as depicted in figure 9.6.
OVP Detection Vgate OTP Detection
Detection Switch Detection Switch: When switch is low SD pin is connected to R SD When switch is high SD pin is connected to a current source ISD
Figure 9.6 : SD Pin Detection Cycles
During an overvoltage monitor cycle the SD pin is connected to a resistance internal to the chip, RSD, to ground and the voltage on the SD pin is observed.
IW3620
ISD
Detection Switch
SD pin VSD-TH R SD
OTP / OVP Fault Detect
Figure 9.7 : Internal Function of SD Pin
Rev. 1.3
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
10.0 Design Example
10.1 Design Procedure
This design example gives the procedure for a flyback converter using IW3620. Refer to Figure 12.1 for the application circuit. The design objectives for this adapter are given in table 10.1. It meets UL, IEC, and CEC requirements.
Determine the Design Specifications (Vout, Iout_max, Vin_max, Vin_min, line, Ripple specification)
10.2 Determine Design Specifications
Parameter Input Voltage Frequency Maximum Output Voltage Nominal Output Voltage Maximum Output Current Nominal Output Current Output Ripple Power Out EPA 2.0 Efficiency Symbol VIN fIN VOUT(max) VOUT(nom) IOUT(max) IOUT(nom) VRIPPLE POUT h Range 90 - 264 VRMS 47 - 64 Hz 24.0 V 21.0 V 0.87 A 0.5 A < 100 mV 20 W 84%
Determine Rvin Resistors
Determine Turns Ratio
Determine Operating VinTon Limit
Determine Magnetizing Inductance
Determine Primary Turns
Table 10.1 : IW3620 Design Specification Table
Determine Secondary Turns
Use equation 10.1 and 10.2 to determine VOUT in the following calculations, where VFD is the forward voltage of the output diode.
Determine Vsense Resistors
Determine Bias Turns and Vcc Capacitance
VOUT ( PCB ) = 110% x VOUT ( nom )
(10.1) (10.2)
No
VOUT = VOUT ( PCB ) + VFD
Can you wind this transformer ?
Yes
Determine Current Sensing Resistor
For this example the nominal VOUT(nom) is 21 V, assuming VFD is 0.5, VOUT is:
VOUT ( PCB ) = 110% x 21V = 23.1
Determine Input Bulk Capacitance
VOUT = 23.1V + 0.5V = 23.6V
Determine Output Capacitance
10.3 input Selection
VIN resistors are chosen primarily to scale down the input voltage for the IC. The default scale factor for the input voltage in the IC is 0.0043 and the internal impedance of this pin is ZIN (5 kW). Therefore, the VIN resistors should equate to:
RVin = Z IN - Z IN 0.0043
Determine Snubber Network
Determine Ton Delay Compensation
Determine SD Pin Components
(10.3)
Finish
Figure 10.1 : Design Procedure
From equation 10.3, ideally RVin should be 1.16 MW. A lower value of RVin can decrease the startup time of the power supply. The value of RVin affects the (VINTON) limits of the IC. IW3620 10/1/09 Page 11
Rev. 1.3
IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
(VIN TON )limit = 0.0043 x Z
720V ms
IN
(RVin + Z IN )
135V ms
10.7 and 10.8) need to be satisfied so that indeed (VINTON)MAX occurs at full load and lowest input voltage. (10.4)
TP (QR min) >
' TP (QR min) >
1 100kHz
(10.7) (10.8)
(VIN TON )limit = 0.0043 x Z
IN
(RVin + Z IN )
(10.5)
1 + TRES 110kHz
For this example RVin is chosen to be 1.12 M therefore,
(VIN TON )limit = 0.0043 x 5k W (VIN TON )limit
720V ms
(1.12M W + 5k W )
= 697V ms
TRES is the VDS resonant period as shown in Figure 10.2. TRES can be estimated to be approximately 2 s as a starting point and then adjusted after the power supply is tested.
Gate
135V ms = 0.0043 x = 131V ms 5k W (1.12 + 5k W )
Keep in mind, by changing RVin to be something other than 1.16 MW the minimum and maximum input voltage for startup also changes. Since the IW3620 uses the exact scaled value of VIN for its calculations, there should be a filter capacitor on the input pin to filter out any noise that may appear on the VIN signal. This is especially important for line in surge conditions.
VDS
TRESET TON TPERIOD
TRES
10.4 Turns Ratio
The maximum allowable turns ratio between the primary and secondary winding is determined by the minimum detectable reset time of the transformer during PFM mode.
NTR (max) = TRESET (min) x VOUT
Figure 10.2 : VDS Timing
When both criterion are met then (VINTON)MAX can be determined by equation 10.9.
(VIN TON )max = f SW (max op) x
where, f SW (max op) = 1 TP (QRmin) 1 VINDC (min) + 1 NTR x VOUT
-1
(VIN TON )PFM
(10.6)
(10.9)
Setting TRESET(min) at 1.5 s,
NTR (max) = 131V ms = 3.70 1.5ms x 23.6V
Where VINDC(min) is the minimum input voltage across the bulk capacitor. Assuming TRES is 2 s then:
TP (QR min) > 10ms
' TP (QR min) >
For this example a turns ratio of 2.5 is chosen. Keep in mind in valley mode switching the higher the turns ratio the lower the VDS turn-on voltage, which means less switch turn-on power loss. Also consider the voltage stress on the MOSFET (VDS) is higher with an increase in turns ratio. The voltage stress on the output diode is lower with an increase in turns ratio respectively.
1 + 2ms = 11.1ms 110kHz
Using 80 V for VINDC(min),
f SW (max op) = 85kHz , and TP = 11.76ms
10.5 Operating Maximum (ViNTON)
Maximum operating VINTON or (VINTON)MAX for valley mode switching is traditionally designed at full load and lowest input voltage. For the IW3620, two constraints (equation Rev. 1.3
(VIN TON )max = 85kHz x
1 1 + 80V 2.5 x 23.6
-1
= 399V ms
Also, to provide enough margin for component values, usually:
(VIN TON )max < (VIN TON )limit x 0.85
(10.10) Page 12
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Digital PWM Current-Mode Controller for AC/DC LED Driver
(VIN TON )max < 697V ms x 0.85 = 592V ms
Since we calculated 399 V*s as our VIN*TON we have enough margin.
10.7 Primary Winding
In order to keep the transformer from saturation, the maximum flux density must not be exceeded. Therefore the minimum primary winding must meet:
N PRI
10.6 Magnetizing inductance
A feature of the IW3620 is the lack of dependence on the magnetizing inductance for the CC curve. Although the constant current limit does not depend on the magnetizing inductance, there are still restrictions on the magnetizing inductance. The maximum LM is limited by the amount of power that needs to come out of the transformer in order for the power supply to regulate. This is given by:
LM (max) =
(VIN TON )max
Bmax x Ae
(10.13)
Where BMAX is maximum allowed flux density and Ae is the core area. From the transformer core datasheet we find that for this example BMAX is 320 mT. For an RM6 core, Ae is 35 mm2.
N PRI 399V ms 320mT x 35mm 2 = 36
(VIN TON )2 x f sw(max op) max
2 x PXFMR (max) VOUT x I OUT hX
(10.11)
For this example, we choose 75 primary turns.
PXFMR (max) =
10.8 Secondary Winding
From the primary winding turns, we obtain the secondary winding.
N SEC = N PRI NTR
Where X is the efficiency of the transformer, for this example we assume it's 87 %.
PXFMR (max) = LM (max) = 23.6V x 0.5 A = 13.6W 0.87 2 x 13.6W = 0.497 mH
(10.14)
(399V ms )2 x 85kHz
Thus, in our example:
N SEC = 75 = 30 2.5
The minimum LM is limited by the maximum allowable peak primary current. VREG-TH corresponds to the maximum ISENSE voltage. See section 10.11 to calculate RIsense. Therefore LM is limited by:
LM (min) = 2 x PXFMR (max ) V f SW (max op) x REG -TH RIsense
2
10.9 Bias Winding and VCC Capacitance
VCC is the supply to the IW3620 and should be below 16 V. The bias winding needs to ensure than VCC does not exceed 16 V during normal operation.
N BIAS = N SEC (VCC + VFD ) VOUT
(10.12)
LM (min) =
2 x 13.6W 85kHz x 1.0V
(10.15)
(
1.1W )
2
= 0.387 mH
Set VCC at around 11 V
N BIAS = 30 (11V + 0.5 ) 23.6 = 15
For this example, we choose LM to be 0.438 mH. If these limits do not give enough tolerance for LM, increasing (VINTON)max can raise the maximum limit on LM. Take care not to go above (VINTON)limit. Also, keep in mind that if equation 10.7 and 10.8 are not met then (VINTON)max does not occur at full load and lowest input voltage, thus some of the equations here would be invalid.
Choose a value for NBIAS to be close to this number, for this example we choose 15 turns. The VCC capacitor (CVcc) stores the VCC charge during IC operation and the controller checks this voltage and makes sure it is within range before starting and operating. The startup time is a function of how quickly this capacitor can charge up.
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Digital PWM Current-Mode Controller for AC/DC LED Driver
tSTART -UP = CVCC x VCC ( ST )
VINAC x 2 RVin
- I INST
VIsense (CC ) =
TPERIOD x KC TRESET
(10.16)
(10.22)
10.10 VSENSE Resistors and Winding
The output voltage regulation is mainly determined by the feedback signal VSENSE.
VSENSE = VOUT _ PCB x K SENSE
For IW3620 KC is 0.5 V, therefore RIsense depends on the maximum output current by;
RIsense = NTR x KC x hX 2 x I OUT ( nom )
(10.23)
(10.17)
Where:
K SENSE RBVsns N = x Vsense (RBVsns + RTVsns ) N SEC
From table 10.1 IOUT(nom) is given to be 0.5 A, therefore RIsense is:
RIsense = 2.5 x 0.5V x 0.87 = 1.08W 2 x 0.5 A
(10.18)
Internally, VSENSE is compared to a reference voltage VSENSE(nom). Where, VSENSE(nom) is 1.538 V.
K SENSE = VSENSE ( nom ) VOUT _ PCB
1.538V = 0.065 23.6V
We recommend using 1% tolerance resistors for RIsense.
10.12 input Bulk Capacitor
The input bulk capacitor, CBULK is chosen to maintain enough input power to sustain constant output power even as the input voltage is dropping. In order for this to be true CBULK must be: 2 x PIN x 0.25 + 21 x arcsin
VINDC (min) 2 xVINAC (min)
(10.19)
K SENSE =
From here we can find the ratio necessary for RBVsns and RTVsns. For this example we set RTVsns to be 20 k. Assuming we use the same winding for both VSENSE and VCC:
0.065 = RBVsns 15 x (RBVsns + 20k W ) 30
CBULK = PIN =
(2 xV
2 INAC (min)
2 - VINDC (min) x fline
)
(10.24)
VOUT (Cable ) x I OUT hpower supply
RBVsns = 3.0k W
At this point the transformer design is complete. This would be a good time to confirm that this transformer is feasible to build.
VINAC(min) is the minimum input voltage (rms) to be inputted into the power supply and fline is the lowest line frequency for the power supply (in this case 47 Hz). VINDC(min) is determined in section 10.5 to be 80 V.
23.6V x 0.5 A = 13.88W 0.85 2 x 13.88W x 0.25 + 21 x arcsin CBULK = 2 x 852 - 802 x 47 PIN =
10.11 Current Sense Resistor
The ISENSE resistor determines the maximum current output of the power supply. The output current of the power supply is determined by:
I OUT = 1 x NTR x I PRI ( pk ) x 2 TRESET x hX TPERIOD
(
)
(
80V 2 x85VAC
) = 22mF
(10.20)
For this example CBULK is chosen to be 47 F.
When the maximum current output is achieved the voltage seen on the ISENSE pin (VIsense) should reach its maximum. Thus, at constant current limit:
I PRI ( pk ) = VIsense (CC ) RIsense
10.13 Output Capacitance
The output capacitance affects both the steady state ripple and the dynamic response of the power supply. Assuming an ideal capacitor where ESR (equivalent series resistance) and ESL (equivalent series inductance) are negligible then:
COUT (Steady State) = QOUT VOUT ( ripple)
(10.21)
Substituting this into equation 10.20 we get:
(10.25) Page 14
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Digital PWM Current-Mode Controller for AC/DC LED Driver
The output capacitor supplies the load current when the secondary current is below the output current.
QOUT = LM x I SEC ( pk ) - I OUT ( nom )
2 2 x NTR x h X x VOUT
VDROP ( sense ) = (1.538V - 1.48V )x
23.6V = 0.890V 1.538V
(
)
2
Plug everything into equation 10.29: (10.26)
COUT (Dynamic ) =
The ISEC(pk) is:
I SEC ( pk ) =
(2V - 0.890V )
0.5 A x 352ms
= 159mF
(VIN TON )MAX
LM
x NTR x h X
(10.27)
Pick the larger capacitance value between COUT(Dynamic) and COUT(Steady State). In this case COUT is chosen to be 470 F.
So to keep VOUT(ripple) to be 100 mV,
I SEC ( pk ) 399V ms = x 2.5 x 0.87 = 1.98 A 0.438mH 0.438mH x (1.98 A - 0.5 A ) 2 x 2.52 x 0.87 x 23.6V 3.74mC = 37mF 100mV
2
10.14 Snubber Network
The snubber network is implemented to reduce the voltage stress on the MOSFET immediately following the turn off of the gate drive. The goal is to dissipate the energy from the leakage inductance of the transformer. For simplicity and a more conservative design first assume the energy of the leakage inductance is only dissipated through the snubber. Thus:
1 2 2 2 2 x Llk x I PRI ( pk ) = 1 x CSNUB x VDS ( pk ) - VDS (val ) 2
QOUT =
= 3.74mC
COUT (Steady State) =
(10.31)
The actual ripple is higher than the above calculations suggest, because the calculations do not include ESR. Assume that the load transient goes from no load to IOUT(HIGH). Then from section 9.5, equation 9.8 we find that the relationship between output capacitance (COUT(Dynamic)) and VDROP(IC) is :
COUT (Dynamic ) = I OUT (HIGH ) x TP (No load) VDROP ( IC )
(10.28)
Llk can be measured from the transformer and VDS is the voltage across the MOSFET. Choose a CSNUB, keeping in mind that the larger the value of CSNUB the lower the voltage stress is on the MOSFET. However, capacitors are more expensive the larger their capacitance. Choose CSNUB based on these two criteria and select VDS(pk) and VDS(val). Now a resistor needs to be selected to dissipate VDS(pk) to VDS(val) during the on-time of the gate driver. The dissipation of this resistor is given by:
VDS (val ) VDS ( pk ) =e
- TP ( min op) RSNUB CSNUB
Then solving for VDROP(IC), where VDynamic(DROP) is the maximum allowable drop in voltage for the design during dynamic response, and VDROP(sense) is the drop in voltage before VSENSE signal is low enough to register a dynamic transient.
COUT (Dynamic ) = I OUT (HIGH ) x TP (No load) VDynamic ( Drop ) - VDROP ( sense )
(10.32)
Using equation 10.32 solve for RSNUB. This gives a conservative estimate of what CSNUB and RSNUB should be. Included in the snubber network is also a resistor in series with a diode. The diode directs current to the snubber capacitor when the MOSFET is turned off; however there is some reverse current that goes through the diode immediately after the MOSFET is turned back on. This reverse current occurs because there is a short period of time when the diode still conducts after switching from forward biased to reverse biased. This conduction distorts the falling edge of the VSENSE signal and affects the operation of the IC. So, the resistor in series with the diode is there to diminish the reverse current that goes through the diode immediately after the MOSFET is turned on.
(10.29)
Where TP(No load) is the maximum period under no load condition, given by equation 10.30:
TP (No load ) = RPreload x (VIN TON )PFM
2 2 x LM x VOUT 2
x hNo load
(10.30)
Assume that we want no more than 2.0 V drop on VOUT(PCB) during load transient from no load to 100% load and the efficiency of the power supply at no load (No load) is 50% , then COUT(Dynamic) is:
TP (No load ) = 20k W x (131V ms )
2
2 x 0.438mH x 23.6V 2
x 0.5 = 352ms
10.15 TON Delay Filter
IW3620 also contains a feature that allows for adjustment to match high line and low line constant current curves. Page 15
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Digital PWM Current-Mode Controller for AC/DC LED Driver
The mismatch in high line and low line is due to the delay from the IC propagation delay, driver turn-on delay, and the MOSFET turn-on delay. The driver turn-on delay maybe further increased by a gate resistor to the MOSFET. To adjust for these delays the IW3620 factors these delays into its calculations and slightly over compensates for them to provide flexibility. RDly and CDly provide extra delay in the circuit to tweak the compensation. To determine values RDly and CDly follow these steps: 1. Measure the difference between high line and low line constant current limit without filter components. 2. Find the curve that best matches this difference from Figure 11.1. 3. Find the LM that matches the power supply, and find the tRC. 4. Find RDly and CDly from equation 10.33
t RC = RDly x CDly
(RNTC +RSD(ext ) )x I SD > VSD-TH
OVP Only
(10.34)
in order not to trigger OTP fault during normal operation.
For the other four cycles, the IW3620 connects the SD pin to RSD to ground (see section 9.13). At the last cycle the IW3620 observes the voltage on the SD pin and detects an OVP fault if the voltage is higher than VSD-TH, 1 V. In order to not trigger OVP fault, assuming 0 V drop across the series diode, RSD(ext) must meet: VOUT _ PCB N SEC x N AUX x RSD < VSD -TH RSD + RSD (ext )
(10.35)
where, RSD = 8.333 k Both OTP and OVP
(10.33)
10.16 SD Protection
The SD pin can be configured to provide three different types of protection: OTP protection, OVP protection and both OVP and OTP Protection. Figure 10.3 shows the three configurations plus the configuration for no OTP and OVP protection.
To find RSD1(ext) so that OVP can be detected, use equation 10.35. To find RSD2(ext) in series with the NTC use equation 10.34. No OTP and OVP If OTP and OVP from the SD pin are not needed, simply place a resistor, RSD(ext) to ground from the SD pin. Make sure RSD(ext) meets equation 10.36 so OTP protection does not trip. RSD (ext ) x I SD > VSD -TH (10.36)
RSD1(ext) SD pin RNTC RSD(ext) (optional) RNTC RSD2(ext) OUTPUT SD pin
Note that this means OVP is not detected through the SD pin; however, OVP from VSENSE pin is still active and the IW3620 still shuts down if overvoltage condition is detected. Since for this example OTP and OVP are not necessary we place a resistor from SD pin to ground and calculate its value from equation 10.36.
RNTC > 1.2V 100mA = 12k W
a) Overtemperature Protection only
b) Overtemperature Protection and Overvoltage Protection SD pin RSD(ext)
RSD(ext) SD pin c) Overvoltage Protection only
d) No Overtemperature Protection and no overvoltage protection
10.17 PCB Layout
In the IW3620, there are two signals that are important to control the output performance; these are the ISENSE signal and the VSENSE signal. The ISENSE resistor should be close to the source of the MOSFET to avoid any trace resistance from contaminating the ISENSE signal. Also, the ISENSE signal should be placed close to the ISENSE pin. The VSENSE signal should be placed close to the transformer to improve the quality of the sensing signal. Also for better output performance all Page 16
Figure 10.3 : SD Pin Application Configurations
OTP Only To detect an overtemperature protection the IW3620 sends a 107 mA current (ISD) to the SD pin every four cycles (see section 9.13). On the last cycle the IW3620 observes the voltage on the SD pin and detects an OTP fault if the voltage is lower than VSD-TH, 1.0 V during normal operation and 1.2 V during startup. So RSD(ext) in series with NTC must meet Rev. 1.3
IW3620 10/1/09
IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
bypass capacitors should be placed close to their respective pins. To reduce EMI, switching loops need to be minimized. These loops include: 1. The input bulk capacitor, primary winding, MOSFET and RIsense loop. 2. The output diode, output capacitor and secondary winding loop. 3. VCC winding and rectifier diode loop.
L VOUT + N
1)
+
2)
+
3)
1 2 3 4
RTN
NC VSENSE VIN SD
VCC 8 OUTPUT 7 ISENSE 6 GND 5
Optional NTC Thermistor
U1 IW3620
Figure 10.4 : Switching Loops
To improve ESD performance provide a low impedance path from the ground pin of the transformer to the ac power source and make sure this path does not go through the IC ground pin. A discharge spark gap helps to transfer ESD and EOS energy from the secondary side of the power supply directly to the external ac power source. In a switch-mode power supply there are several ground signals, namely: the power ground, the switching ground and the control logic ground. These ground signals should be connected by a star connection. Ground traces should be kept as short as possible. A thick trace on the switching ground helps to lessen switching losses.
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
11.0 Performance Characteristics
120
IOUT (Note1) 50 mA 40 mA 30 mA 20 mA 10 mA
(RDly x CDly), RC (ns)
100 80 60 40 20 0 0.0
0.5
Magnetizing Inductance LM (mH)
1.0
1.5
2.0
2.5
3.0
Figure 10.5 : TON Compensation Chart
12.0 Application Circuit
L 2 A / 250 V 470 H 10 k N Cbulk 0.1 F + Cbulk 47 F + Rvin 560 k Rvin 560 k + Cvcc 4.7 F Rsnub 120 k 0 Csnub 10 nF Cout + 470 F Rpreload 20 k VOUT
470 pF
10 RTN
Rtvsns 20 k Rbvsns 3.0 k 68 pF
1 2 3 4
NC VSENSE VIN SD
VCC 8 OUTPUT 7 ISENSE 6 GND 5
Rgate 10
Rntc 20 k
U1 IW3620
Rdly 1 k Cdly 270 pF
Risense 1.1
Figure 12.1 : Typical Application Circuit
Note 1: IOUT refers to the difference in constant current limit between 264 Vac and 90 Vac when no RDLY and CDLY are applied.
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Digital PWM Current-Mode Controller for AC/DC LED Driver
13.0 Physical Dimensions
8-Lead Small Outline (SOIC) Package
D Symbol M
5 8
Inches
MIN 0.051 0.0020 0.014 0.007 0.189 0.150 0.228 0.086 0.118 0.016 0 MAX 0.067 0.0060 0.019 0.010 0.197 0.157 0.244 0.094 0.126 0.050 8
Millimeters
MIN 1.30 0.05 0.36 0.18 4.80 3.81 5.79 2.18 3.00 0.41 MAX 1.70 0.150 0.48 0.25 5.00 3.99 6.20 2.39 3.20 1.27
8
5 4
E
1
H
N
4 1
A A1 EXPOSED PAD B C D E e H L N M L
e TOP VIEW A1
BOTTOM VIEW
0.050 BSC
1.27 BSC
A B SEATING PLANE SIDE VIEWS C
COPLANARITY 0.10 (0.004)
Figure 13.1 : Physical dimensions, 8-lead SOIC package
Compliant to JEDEC Standard MS12F Controlling dimensions are in inches; millimeter dimensions are for reference only This product is RoHS compliant and Halide free. Soldering Temperature Resistance: [a] Package is IPC/JEDEC Std 020D Moisture Sensitivity Level 3 Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 mm per side. The package top may be smaller than the package bottom. Dimensions D and E are determined at the outermost extremes of the plastic bocy exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body.
14.0 Ordering information
Part Number IW3620-00 Package SOIC-8 Description Tape & Reel1
Note 1: Tape & Reel packing quantity is 2,500/reel.
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IW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
About iWatt
iWatt Inc. is a fabless semiconductor company that develops intelligent power management ICs for computer, communication, and consumer markets. The company's patented pulseTrainTM technology, the industry's first truly digital approach to power system regulation, is revolutionizing power supply design.
Trademark information
(c) 2008 iWatt, Inc. All rights reserved. iWatt, the iW light bulb, EZ-EMI and pulseTrain are trademarks of iWatt, Inc. All other trademarks and registered trademarks are the property of their respective companies.
Contact information
Web: http://www.iwatt.com E-mail: info@iwatt.com Phone: 408-374-4200 Fax: 408-341-0455 iWatt Inc. 101 Albright Way Los Gatos CA 95032-1827
Disclaimer
iWatt reserves the right to make changes to its products and to discontinue products without notice. The applications information, schematic diagrams, and other reference information included herein is provided as a design aid only and are therefore provided as-is. iWatt makes no warranties with respect to this information and disclaims any implied warranties of merchantability or non-infringement of third-party intellectual property rights. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). IWATT SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS, OR OTHER CRITICAL APPLICATIONS. Inclusion of iWatt products in critical applications is understood to be fully at the risk of the customer. Questions concerning potential risk applications should be directed to iWatt, Inc. iWatt semiconductors are typically used in power supplies in which high voltages are present during operation. High-voltage safety precautions should be observed in design and operation to minimize the chance of injury.
Rev. 1.3
IW3620 10/1/09
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